1. Field of the Invention
The present invention generally relates to divide-by-N circuits for dividing the frequency of a master clock signal in order to obtain a clock signal having a different frequency from that of the master clock signal. The present invention more particularly relates to a high-speed programmable divider capable of providing an output clock signal having an even duty cycle and a programmable delay chain.
2. Background Art
Divider circuits are well-known circuits that are used to divide the frequency of a clock signal (e.g., a system clock) by a specific number of counts. That is, for N clock pulses input into the circuit, only one output pulse is generated.
These divider circuits are used for a number of different applications. In particular, divider circuits are used to reduce the overall number of oscillators required on a given semiconductor chip, thereby making available additional room on the chip to place as much other circuitry as possible. Voltage control oscillators (VCOs), for example, are commonly used in phase lock loop (PLL) circuits. Often, a single VCO circuit is provided that generates a master clock signal. One or more divider circuits may then be used to generate clock signals having different frequencies.
Typically, one or more divide-by-2 circuits are used to divide the master clock signal frequency by a factor of 2, 4, 8, etc. More particularly, most conventional divider circuits divide the master clock signal frequency by a divide ratio that is a power of 2. These conventional divider circuits normally comprise a number of D flip flops, which may be configured for use in a divider circuit by tying the Q bar to D. One D flip flop configured in this manner equates to divide by 2. Two flip flops equates to divide by 4, and three flip flops equates to divide by 8, and so on.
On the other hand, other types of divider circuits may be easily configured to accommodate any single divide ratio, regardless of whether the particular ratio is a power of 2 or not. The Johnson counter is one such device and may be configured to accommodate any divide ratio (e.g., 2, 3, 4, 5, or 6). For this reasons, Johnson counters are often among the most commonly used counters in divider circuits.
One problem with divider circuits using conventional counters, such as the Johnson counter, is that each circuit must be configured in accordance with only one divide ratio. That is, a particular divider circuit may only be configured to accommodate a divide ratio of 2, 3, or 4, etc., and not 2, 3, and 4. Further, although the Johnson counter is desirably because of its ability to accommodate any single divide ratio, it produces a signal having undesirable duty cycles. For example, most modem PLLs, as well as other high-speed applications, require clock signals having duty cycles on the order of about 50%. Typical Johnson counters, however, produce signals having much higher duty cycles.
What is needed, therefore, is a divider circuit reconfigurable to accommodate a variety of different frequency divide ratios. In addition, it would be desirable to have such a divider circuit that produces an output signal having a duty cycle suitable for high-speed applications, preferably on the order of about 50%. Further still, it would be desirable to have a divider circuit capable of selectively delaying the output clock signal to resolve timing issues.
According to an aspect of the invention, a programmable divider circuit is provided that divides a master clock frequency by a factor to provide an output clock signal whose frequency is equal to the frequency of the master clock signal divided by that factor.
Consistent with the principles of the present invention as embodied and broadly described herein, the invention includes a programmable divider comprising a synchronous counter. The synchronous counter is configured to receive input clock signals and produce output signals responsive thereto. The programmable divider also comprises a control circuit coupled to the synchronous counter to form a feedback loop therewith. The control circuit is configurable to (i) selectively receive selected ones of the output signals and (ii) control divide characteristics associated with the synchronous counter based upon the selected output signals.
In another embodiment, the invention is directed to a method to control a divide ratio of a divider circuit. The method comprises receiving in a synchronous counter a first clock input signal and a first data signal, the first data signal being produced as an output from a first type logic gate. The receiving produces respective synchronous counter output signals. The method also comprises providing the respective synchronous counter output signals to selected inputs of N number of second type logic gates, wherein other inputs of the second type logic gates form N number of clock output ports. Each second type logic gate provides an intermediate signal as an output. One of the inputs of a first of the second type logic gates (i) is coupled to a first input of the first type logic gate and (ii) forms a first of the N number of clock output ports. Next, the method comprises respectively providing the N number of intermediate signals to N number of multiplexer inputs.
The multiplexer (i) produces multiplexer output signals based upon selected ones of the N number of inputs, (ii) supplies multiplexer output signals to a second input of the first type logic gate in accordance with the selected ones of the multiplexer inputs, and (iii) produces clock output signals at selected ones of the N number of clock output ports based upon the supplied multiplexer output signals. Finally, included is providing a control signal to a control signal port of the multiplexer to determine the selected ones of the N number of multiplexer inputs.
Features and advantages of the invention include providing a user with the capability to program a single divider circuit to accommodate a variety of different divide ratios. Such a capability may be particularly useful in dynamic high-speed applications which call for different divide ratios throughout different aspects of the application. On such application may be a PLL configured to run at different speeds within a given circuit. These applications conventionally require dedicated divider circuits having predetermined divide ratios, which may lead to increased device production costs. Further, the additional circuit components may contribute to higher system failure rates.
Furthermore, the ability to convert the duty cycle of output signals to duty cycle values more suitable for higher speed applications expands the utility of conventional Johnson counters. This increased capability, realized through implementation of preferred embodiments of the present invention, eliminates the need to waste limited silicon real estate to accommodate other circuit components specifically dedicated to performing this task.